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Regulations on the Protection of Topographies of Semiconductor Products and Regulations supplementing the Regulations on the Protection of Topographies of Semiconductor Products (OG Nos. 72/2004 & 117/2007), Croatia
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Superseded Text
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Year of Version
2007
Dates
Entry into force:
June 1, 2004
Adopted:
June 1, 2004
Type of Text
Implementing Rules/Regulations
Subject Matter
Layout Designs of Integrated Circuits,
Undisclosed Information (Trade Secrets)
Notes
The notification by Croatia to the WTO under Article 63.2 of TRIPS states:
'Regulations contain detailed granting procedures for layout-design (topography) of integrated circuits before the State Intellectual Property Office.'
Available Texts
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Main text(s)
English
Regulations on the Protection of Topographies of Semiconductor Products and Regulations supplementing the Regulations on the Protection of Topographies of Semiconductor Products (OG Nos. 72/2004 & 117/2007)
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Legislation
Is superseded by (1 text(s))
Is superseded by (1 text(s))
WTO Document Reference
IP/N/1/HRV/L/3
IP/N/HRV/O/6
IP/N/1/HRV/5
WIPO Lex No.
HR048