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Regulation No. 15 of the Minister of Justice of January 3, 2012, on the Requirements for the Format and the Procedure for Filing of Registration Application Documents of the Layout-Design of Integrated Circuits, Estonia
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Latest Version in WIPO Lex
Year of Version
2012
Dates
Entry into force:
January 13, 2012
Adopted:
January 3, 2012
Type of Text
Implementing Rules/Regulations
Subject Matter
Layout Designs of Integrated Circuits,
Undisclosed Information (Trade Secrets),
IP Regulatory Body
Available Texts
Main text(s)
Main text(s)
Estonian
Justiitsminister 3. jaanuar 2012. a määrus nr 15 'Mikrolülituse topoloogia registreerimise taotluse dokumentide vorminõuded ja esitamise kord'
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Legislation
Implements (1 text(s))
Implements (1 text(s))
WIPO Lex No.
EE197