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Protection of Layout-Designs (Topographies) of Integrated Circuits Act (Chapter 256, Act No. 15 of 2000, Revised Edition 2000), Belize
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Year of Version
2000
Dates
Assented:
June 21, 2000
Type of Text
Main IP Laws
Subject Matter
Layout Designs of Integrated Circuits
Available Texts
Main text(s)
Main text(s)
English
Protection of Layout-Designs (Topographies) of Integrated Circuits Act (Chapter 256, Act No. 15 of 2000, Revised Edition 2000)
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Related Legislation
Is superseded by (1 text(s))
Is superseded by (1 text(s))
WTO Document Reference
IP/N/1/BLZ/L/2
WIPO Lex No.
BZ004