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Ordinance No. 20 of January 26, 1993 of the President of the Patent Office of the Republic of Poland on the Protection of Topographies of Integrated Circuits, Poland
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Year of Version
1993
Dates
Entry into force:
January 28, 1993
Issued:
January 26, 1993
Type of Text
Implementing Rules/Regulations
Subject Matter
Layout Designs of Integrated Circuits
Notes
Date of entry into force of the law: See Article 23 for further detail.
Available Texts
Main text(s)
Main text(s)
English
Ordinance No. 20 of January 26, 1993 of the President of the Patent Office of the Republic of Poland on the Protection of Topographies of Integrated Circuits
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WTO Document Reference
IP/N/1/POL/L/1
WIPO Lex No.
PL008