Poland

Ordinance No. 20 of January 26, 1993 of the President of the Patent Office of the Republic of Poland on the Protection of Topographies of Integrated Circuits

Year of current version:1993
Date of entry into force of original text:January 28, 1993
Date of Text (Issued):January 26, 1993
Type of Text:Implementing Rules/Regulations
Subject Matter:Layout Designs of Integrated Circuits
Notes:Date of entry into force of the law: See Article 23 for further detail.
Available Texts: 
English

Ordinance No. 20 of January 26, 1993 of the President of the Patent Office of the Republic of Poland on the Protection of Topographies of Integrated Circuits Ordinance No. 20 of January 26, 1993 of the President of the Patent Office of the Republic of Poland on the Protection of Topographies of Integrated Circuits, Complete document (pdf) [61 KB] Ordinance No. 20 of January 26, 1993 of the President of the Patent Office of the Republic of Poland on the Protection of Topographies of Integrated Circuits, Complete document (html) [30 KB] (Version with Automatic Translation Tool)

WIPO Lex No.:PL008

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