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Regulation No. 17 of the Minister of Justice of January 3, 2012, on the Procedure for Access to and Release of Information from the Register of Layout-Designs of Integrated Circuits (consolidated text of June 3, 2013), Estonia
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Year of Version
2013
Dates
Entry into force:
January 13, 2012
Adopted:
January 3, 2012
Type of Text
Implementing Rules/Regulations
Subject Matter
Layout Designs of Integrated Circuits,
IP Regulatory Body
Available Texts
Main text(s)
Main text(s)
Estonian
Justiitsminister 3. jaanuar 2012. a määrus nr 17 'Mikrolülituste topoloogiate registriga tutvumise ja registrist teabe väljastamise kord' (konsolideeritud tekst 03.06.2013)
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Legislation
Implements (1 text(s))
Implements (1 text(s))
WIPO Lex No.
EE193