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Rules for the Preparation, Filing, and Examination of an Application for the Registration of a Layout-Design of Integrated Circuits, Tajikistan

(approved by Order No. 6 of March 28, 2007, of the Ministry of Economic Development and Trade)

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Details Details Year of Version 2007 Dates Issued: March 28, 2007 Type of Text Implementing Rules/Regulations Subject Matter Layout Designs of Integrated Circuits

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Main text(s) Main text(s) Tajik Қоидаҳои тартибдиҳӣ, пешниҳод ва баррасии ариза дар бораи бақайдгирии топологияи микросхемаи интегралӣ (Бо фармоиши Вазорати иқтисод ва савдои Ҷумҳурии Тоҷикистон аз 28 марти 2007, № 6 тасдиқ карда шудааст)      Russian Правила составления, подачи и рассмотрения заявки на регистрацию топологии интегральной микросхемы     
 
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Правила составления, подачи и рассмотрения заявки на регистрацию топологии интегральной микросхемы
 
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Қоидаҳои тартибдиҳӣ, пешниҳод ва баррасии ариза дар бораи бақайдгирии топологияи микросхемаи интегралӣ (Бо фармоиши Вазорати иқтисод ва савдои Ҷумҳурии Тоҷикистон аз 28 марти 2007, № 6 тасдиқ карда шудааст)

Legislation Implements (1 text(s)) Implements (1 text(s))
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WIPO Lex No. TJ022