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Layout-Designs of Integrated Circuits Protection Act, Estonia

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Superseded Text  Go to latest Version in WIPO Lex
Year of Version 1999 Dates Entry into force: March 16, 1999 Adopted: November 25, 1998 Type of Text Main IP Laws Subject Matter Layout Designs of Integrated Circuits, Undisclosed Information (Trade Secrets), Enforcement of IP and Related Laws, IP Regulatory Body Notes The notification by Estonia to the WTO under article 63.2 of TRIPS states:
'The Act prohibits disclosure of information without the consent of the applicant for microcircuits topography in certain circumstances.'

For date of entry into force, see Section 69 for further details.

Available Texts Main text(s) Main text(s) Estonian Mikrolülituse topoloogia kaitse seadus PDF HTML French Loi sur la protection des schémas de configuration de circuits intégrés PDF HTML English Layout-Designs of Integrated Circuits Protection Act PDF HTML
Legislation Is implemented by (1 text(s)) Is implemented by (1 text(s))
Regulation of the Minister of Economic Affairs on Confirming Implementing Regulations Derived from the Layout-Design of Integrated Circuit Protection Act of 4 March 1999 (EE050)
 Is superseded by (4 text(s)) Is superseded by (4 text(s))
Layout-Designs of Integrated Circuits Protection Act (consolidated text of August 31, 2023) (EE247)
Layout-Designs of Integrated Circuits Protection Act (consolidated text of April 1, 2019) (EE230)
Layout-Designs of Integrated Circuits Protection Act (consolidated text of January 1, 2015) (EE156)
Layout-Designs of Integrated Circuits Protection Act (consolidated text of January 1, 2012) (EE121)
Treaties
WTO Document Reference
IP/N/1/EST/L/1
WIPO Lex No. EE008