Estonia

Layout-Designs of Integrated Circuits Protection Act

Year of Version:1999
Date of Entry into Force:March 16, 1999
Date of Text (Enacted):November 25, 1998
Type of Text:Main IP Laws: enacted by the Legislature
Subject Matter:Enforcement of IP and Related Laws, IP Regulatory Body, Layout Designs of Integrated Circuits, Undisclosed Information (Trade Secrets)
Notes:The notification by Estonia to the WTO under article 63.2 of TRIPS states:
'The Act prohibits disclosure of information without the consent of the applicant for microcircuits topography in certain circumstances.'

For date of entry into force, see Section 69 for further details.
Available Texts: 
English

Layout-Designs of Integrated Circuits Protection Act Layout-Designs of Integrated Circuits Protection Act, Complete document (pdf) [344 KB]

Estonian

Mikrolülituse topoloogia kaitse seadus Mikrolülituse topoloogia kaitse seadus, Complete document (pdf) [125 KB] Mikrolülituse topoloogia kaitse seadus, Complete document (htm) [54 KB] (Version with Automatic Translation Tool)

French

Loi sur la protection des schémas de configuration de circuits intégrés Loi sur la protection des schémas de configuration de circuits intégrés, Complete document (pdf) [345 KB]

Related Legislation:
Related Treaties:
WIPO Lex No.:EE008

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