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Search result: 2 of 841 |
(WO/2009/012111) METHOD FOR FABRICATING DUAL DAMASCENE PROFILES USING SUB PIXEL-VOTING LITHOGRAPHY AND DEVICES MADE BY SAME
- Biblio. Data
- Description
- Claims
- National Phase
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| Latest bibliographic data on file with the International Bureau
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| IPC: | H01L 21/4763 (2006.01), H01L 27/108 (2006.01) | |||||||||||
| Applicants: | THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS [US/US]; 352 Henry Administration Building, 506 South Wright Street, Urbana, Illinois 61801 (US) (All Except US). JAIN, Kanti [US/US]; (US) (US Only). REDDY, Uttam [IN/US]; (US) (US Only). | |||||||||||
| Inventors: | JAIN, Kanti; (US). REDDY, Uttam; (US). | |||||||||||
| Agent: | BARONE, Stephen B. et al.; Greenlee, Winner And Sullivan, P.C., 4875 Pearl East Circle, Suite 200, Boulder, Colorado 80301 (US). | |||||||||||
| Priority Data: |
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| Title: | METHOD FOR FABRICATING DUAL DAMASCENE PROFILES USING SUB PIXEL-VOTING LITHOGRAPHY AND DEVICES MADE BY SAME | |||||||||||
| Abstract: | This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The present invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication methods for making integrated electronics, and can be effectively integrated into existing photolithographic, etching, and thin film deposition patterning systems, processes and infrastructure. | |||||||||||
| Designated States: |
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. African Regional Intellectual Property Org. (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW) Eurasian Patent Organization (EAPO) (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM) European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR) African Intellectual Property Organization (OAPI) (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG). | |||||||||||
| Publication Language: | English (EN) |
| Filing Language: | English (EN) |
