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(WO/1999/003106) METHOD AND APPARATUS FOR ADAPTIVELY ADJUSTING THE TIMING OF A CLOCK SIGNAL USED TO LATCH DIGITAL SIGNALS, AND MEMORY DEVICE USING SAME
- Biblio. Data
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| Latest bibliographic data on file with the International Bureau
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| IPC: | G11C 7/10 (2006.01), G11C 7/22 (2006.01) | ||||||||||||||||||
| Applicant: | MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way P.O. Box 6 Boise, ID 83707-0006 (US). | ||||||||||||||||||
| Inventors: | BAKER, Russel, Jacob; (US). MANNING, Troy, A.; (US). | ||||||||||||||||||
| Agents: | BULCHIS, Edward, W. et al.; Seed and Berry LLP
6300 Columbia Center
701 Fifth Avenue
Seattle, WA 98104-7092 (US). Hirsch Peter; Klunker.Schmitt-Nilson.Hirsch Winzererstrasse 106 D-80797 München Germany (DE). | ||||||||||||||||||
| Priority Data: |
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| Title: | METHOD AND APPARATUS FOR ADAPTIVELY ADJUSTING THE TIMING OF A CLOCK SIGNAL USED TO LATCH DIGITAL SIGNALS, AND MEMORY DEVICE USING SAME | ||||||||||||||||||
| Abstract: | A system for adjusting the phase of an internal clock signal relative to an external clock signal in a packetized dynamic random access memory device. The system applies a plurality of initialization packets to the memory device that are captured in a shift register responsive to a transition of the internal clock signal. However, the phase of the internal clock signal is sequentially incremented after each initialization packet has been captured in the shift register. After a plurality of initialization packets have been captured, an evalution circuit identifies which phases of the internal clock signal clocked the shift register at the proper time to accurately capture each initialization packet. A single phase of the internal clock signal is then selected from within the range of internal clock signal phases that successfully captured initialization packets. This selected phase of the internal clock signal is used during normal operation of the memory device. | ||||||||||||||||||
| Designated States: |
AL, AM, AT, AU, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, GH, GM, GW, HU, ID, IL, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, UZ, VN, YU, ZW. African Regional Intellectual Property Org. (ARIPO) (GH, GM, KE, LS, MW, SD, SZ, UG, ZW) Eurasian Patent Organization (EAPO) (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM) European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE) African Intellectual Property Organization (OAPI) (BF, BJ, CF, CG, CI, CM, GA, GN, ML, MR, NE, SN, TD, TG). | ||||||||||||||||||
| Publication Language: | English (EN) |
| Filing Language: | English (EN) |
