Marks and Layout-Designs (Topographies) of Integrated Circuits Incorporated in the TRIPS Agreement

Document CodeWIPO-WTO/IP/DAR/02/5/B(I)
Related Meeting(s)WIPO-WTO/IP/DAR/02
Publication DateApr 11, 2002
English Marks and Layout-Designs (Topographies) of Integrated Circuits Incorporated in the TRIPS Agreement
Français Les marques et les schémas de configuration (topographies) de circuits intégrés dans l'Accord sur les ADPIC