IPC 6 English version G06F 9/00-G06F 13/42

G06F00900-G06F01342

SECTION G– PHYSICS

G 06

COMPUTING; CALCULATING; COUNTING (score computers for games A 63 B 71/06, A 63 D 15/20, A 63 F 1/18; combinations of writing implements with computing devices B 43 K 29/08)

G 06 F

ELECTRIC DIGITAL DATA PROCESSING (computers in which a part of the computation is effected hydraulically or pneumatically G 06 D, optically G 06 E; self-contained input or output peripheral equipment G 06 K; impedance networks using digital techniques H 03 H)

Arrangements for programme control, e.g. control unit (programme control for peripheral devices G 06 F 13/10; in regulating or control systems G 05 B) [4]

using wired connections, e.g. plugboard

using record carriers containing only programme instructions (G 06 F 9/06 takes precedence)

using stored programme, i.e. using internal store of processing equipment to receive and retain programme

Micro-control or micro-programme arrangements [3]

Loading of the micro-programme [3]

Address formation of the next micro-instruction (G 06 F 9/28 takes precedence) [3]

Enhancement of operational speed, e.g. by using several micro-control devices operating in parallel [3]

Arrangements for executing machine- instructions, e.g. instruction decode (for executing micro-instructions G 06 F 9/22; for executing subprogrammes G 06 F 9/40) [3]

302

Controlling the executing of arithmetic operations [5]

305

Controlling the executing of logical operations [5]

308

Controlling single bit operations (G 06 F 9/305 takes precedence) [5]

312

Controlling loading, storing or clearing operations [5]

315

Controlling moving, shifting or rotation operations [5]

318

with operation extension or modification [5]

Address formation of the next instruction, e.g. incrementing the instruction counter, jump (G 06 F 9/38 takes precedence; subprogramme jump G 06 F 9/42) [3]

Addressing or accessing the instruction operand or the result (address translation G 06 F 12/00) [3,5]

345

of multiple operands or results [5]

Indirect addressing [5]

355

Indexed addressing [5]

Concurrent instruction execution, e.g. pipeline, look ahead [3]

Arrangements for executing subprogrammes, i.e. combinations of several instructions [3]

Formation of subprogramme-jump address or of return address [3]

Arrangements for executing specific programmes [3]

445

Programme loading or initiating [5]

Compilation or interpretation of high level programme languages [5]

455

Emulation; Software simulation [5]

Multiprogramming arrangements, e.g. using interrupt; Priority circuits therefor [3]

11/

Error detection; Error correction; Monitoring (methods or arrangements for verifying the correctness of marking on a record carrier G 06 K 5/00; in information storage based on relative movement between record carrier and transducer G 11 B, e.g. G 11 B 20/18; in static stores G 11 C; coding, decoding or code conversion, for error detection or error correction, in general H 03 M 13/00) [4]

11/

Error detection or correction by redundancy in data representation, e.g. by using checking codes

11/

Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

11/

Error detection or correction of the data by redundancy in operation (G 06 F 11/16 takes precedence) [3]

11/

Error detection or correction of the data by redundancy in hardware [3]

11/

using passive fault-masking of the redundant circuits, e.g. by quadding or by majority decision circuits [3]

11/

using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements [3]

11/

Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing (testing of digital circuits, e.g. of separate computer components, G 01 R 31/317) [3]

11/

Marginal testing [3]

11/

Testing of logic operation, e.g. by logic analysers [6]

11/

Functional testing [3]

11/

263

Generation of test inputs, e.g. test vectors, patterns or sequences [6]

11/

267

Reconfiguring circuits for testing, e.g. LSSD, partitioning [6]

11/

Built-in tests [6]

11/

273

Tester hardware, i.e. output processing circuits [6]

11/

277

with comparison between actual response and known fault-free response [6]

11/

by checking the correct order of processing (G 06 F 11/08 to G 06 F 11/277 take precedence; monitoring patterns of pulse trains H 03 K 5/19) [3]

11/

Monitoring [3]

11/

with visual indication of the functioning of the machine [3]

11/

Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation [3]

12/

Accessing, addressing or allocating within memory systems or architectures (information storage in general G 11) [4,5]

12/

Addressing or allocation; Relocation (programme address sequencing G 06 F 9/00; arrangements for selecting an address in a digital store G 11 C 8/00) [4]

12/

Addressing variable-length words or parts of words [4]

12/

Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication (G 06 F 12/08 takes precedence) [4]

12/

in hierarchically structured memory systems, e.g. virtual memory systems [4]

12/

Address translation [4]

12/

Replacement control [4]

12/

Protection against unauthorised use of memory [4]

12/

Protection against loss of memory contents [4]

13/

Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G 06 F 3/00; multi-processor systems G 06 F 15/16; transmission of digital information in general H 04 L; selecting H 04 Q) [4]

13/

Programme control for peripheral devices (G 06 F 13/14 to G 06 F 13/42 take precedence) [4]

13/

using hardware independent of the central processor, e.g. channel or peripheral processor [4]

13/

Handling requests for interconnection or transfer [4]

13/

for access to memory bus (G 06 F 13/28 takes precedence) [4]

13/

with priority control [4]

13/

for access to input/output bus [4]

13/

using successive scanning, e.g. polling (G 06 F 13/24 takes precedence) [4]

13/

using interrupt (G 06 F 13/32 takes precedence) [4]

13/

with priority control [4]

13/

using burst mode transfer, e.g. direct memory access, cycle steal (G 06 F 13/32 takes precedence) [4]

13/

with priority control [4]

13/

using combination of interrupt and burst mode transfer [4]

13/

with priority control [4]

13/

for access to common bus or bus system [4]

13/

362

with centralised access control [5]

13/

364

using independent requests or grants, e.g. using separated request and grant lines [5]

13/

366

using a centralised polling arbiter [5]

13/

368

with decentralised access control [5]

13/

using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing [5]

13/

372

using a time-dependent priority, e.g. individually loaded time counters or time slot [5]

13/

374

using a self-select method with individual priority code comparator [5]

13/

376

using a contention resolving method, e.g. collision detection, collision avoidance [5]

13/

378

using a parallel poll method [5]

13/

Information transfer, e.g. on bus (G 06 F 13/14 takes precedence) [4]

13/

Bus structure [4]

13/

Bus transfer protocol, e.g. handshake; Synchronisation (synchronisation in transmission of digital information in general H 04 L 7/00) [4]

G06F - G06F 7/72

G06F 15/00 - G06F 171:00