(0)G11C:0/1:
IPC6
SECTION G - PHYSICS
STATIC STORES
G11C
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<<   >>   G11C005/00 - G11C011/56  

G 11 C

STATIC STORES (information storage based on relative movement between record carrier and transducer G 11 B; semiconductor devices for storage H 01 L, e.g. H 01 L 27/108 to H 01 L 27/115; pulse technique in general H 03 K, e.g. electronic switches H 03 K 17/00)
 

Notes

(1)

This subclass covers devices or arrangements for storage of digital or analogue information:
 

(i)

in which no relative movement takes place between an information storage element and a transducer;
 

(ii)

which incorporate a selecting-device for writing-in or reading-out the information into or from the store.

(2)

This subclass does not cover elements not adapted for storage and not provided with such means as referred to in Note (3) below, which elements are classified in the appropriate subclass, e.g. of H 01, H 03 K.

(3)

In this subclass, a storage element is provided with means for writing-in and reading-out at least one item of information.

 

 

 

 

5
/ 00 Details of stores covered by group G 11 C 11/00

5
/ 02 Disposition of storage elements, e.g. in the form of a matrix array  

5
/ 04 Supports for storage elements; Mounting or fixing of storage elements on such supports  

5
/ 05 Supporting of cores in matrix [2]  

5
/ 06 Arrangements for interconnecting storage elements electrically, e.g. by wiring  

5
/ 08 for interconnecting magnetic elements, e.g. toroidal cores  

5
/ 10 for interconnecting capacitors  

5
/ 12 Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores  

5
/ 14 Power supply arrangements (in general G 05 F, H 02 J, H 02 M) [5]  
 

7
/ 00 Arrangements for writing information into, or reading information out from, a digital store (G 11 C 5/00 takes precedence; for stores using transistors G 11 C 11/407, G 11 C 11/413) [2,5]

7
/ 02 with means for avoiding parasitic signals  

7
/ 04 with means for avoiding disturbances due to temperature effects  

7
/ 06 Adaptations of amplifiers (amplifiers per se H 03 F, H 03 K)  
 

8
/ 00 Arrangements for selecting an address in a digital store (for stores using transistors G 11 C 11/407, G 11 C 11/413) [2,5]

8
/ 02 using selecting matrix [2]  

8
/ 04 using a sequential addressing device, e.g. shift register, counter [5]  
 

11
/ 00 Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (G 11 C 14/00 to G 11 C 21/00 take precedence) [5]

Note

 

Group G 11 C 11/56 takes precedence over groups G 11 C 11/02 to G 11 C 11/54. [2]

11
/ 02 using magnetic elements  

11
/ 04 using storage elements having cylindrical form, e.g. rod, wire (G 11 C 11/12, G 11 C 11/14 take precedence) [2]  

11
/ 06 using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element  

11
/ 061 using elements with single aperture or magnetic loop for storage, one element per bit, and for destructive read-out [2]  

11
/ 063 bit-organized, such as, 2L/2D-, 3D-organization, i.e. for selection of an element by means of at least two coincident partial currents both for reading and for writing [2]  

11
/ 065 word-organized, such as 2D-organization, or linear selection, i.e. for selection of all the elements of a word by means of a single full current for reading [2]  

11
/ 067 using elements with single aperture or magnetic loop for storage, one element per bit, and for non-destructive read-out [2]  

11
/ 08 using multi-aperture storage elements, e.g. using transfluxors; using plates incorporating several individual multi-aperture storage elements (G 11 C 11/10 takes precedence; using multi-aperture plates in which each individual aperture forms a storage element G 11 C 11/06) [2]  

11
/ 10 using multi-axial storage elements  

11
/ 12 using tensors; using twistors, i.e. elements in which one axis of magnetisation is twisted  

11
/ 14 using thin-film elements  

11
/ 15 using multiple magnetic layers (G 11 C 11/155 takes precedence) [2]  

11
/ 155 with cylindrical configuration [2]  

11
/ 16 using elements in which the storage effect is based on magnetic spin effect  

11
/ 18 using Hall-effect devices  

11
/ 19 using non-linear reactive devices in resonant circuits [2]  

11
/ 20 using parametrons [2]  

11
/ 21 using electric elements [2]  

11
/ 22 using ferroelectric elements [2]  

11
/ 23 using electrostatic storage on a common layer, e.g. Forrester-Haeff tubes (G 11 C 11/22 takes precedence) [2]  

11
/ 24 using capacitors (G 11 C 11/22 takes precedence; using a combination of semiconductor devices and capacitors G 11 C 11/34, e.g. G 11 C 11/40) [2,5]  

11
/ 26 using discharge tubes [2]  

11
/ 28 using gas-filled tubes [2]  

11
/ 30 using vacuum tubes (G 11 C 11/23 takes precedence) [2]  

11
/ 34 using semiconductor devices [2]  

11
/ 36 using diodes, e.g. as threshold elements [2]  

11
/ 38 using tunnel diodes [2]  

11
/ 39 using thyristors [5]  

11
/ 40 using transistors [2]  

11
/ 401 forming cells needing refreshing or charge regeneration [5]  

11
/ 402 with charge regeneration individual to each memory cell, i.e. internal refresh [5]  

11
/ 403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh [5]  

11
/ 404 with one charge-transfer gate, e.g. MOS transistor, per cell [5]  

11
/ 405 with three charge-transfer gates, e.g. MOS transistors, per cell [5]  

11
/ 406 Management or control of the refreshing or charge-regeneration cycles [5]  

11
/ 407 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing, for memory cells of the field-effect type (in general G 11 C 5/00 to G 11 C 8/00) [5]  

11
/ 408 Address circuits [5]  

11
/ 409 Read-write circuits [5]  

11
/ 41 forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger [5]  

11
/ 411 using bipolar transistors only [5]  

11
/ 412 using field-effect transistors only [5]  

11
/ 413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction (in general G 11 C 5/00 to G 11 C 8/00) [5]  

11
/ 414 for memory cells of the bipolar type [5]  

11
/ 415 Address circuits [5]  

11
/ 416 Read-write circuits [5]  

11
/ 417 for memory cells of the field-effect type [5]  

11
/ 418 Address circuits [5]  

11
/ 419 Read-write circuits [5]  

11
/ 42 using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled  

11
/ 44 using super-conductive elements, e.g. cryotron [2]  

11
/ 46 using thermoplastic elements  

11
/ 48 using displaceable coupling elements, e.g. ferromagnetic cores, to produce change between different states of mutual or self-inductance  

11
/ 50 using actuation of electric contacts to store the information (mechanical stores G 11 C 23/00; switches providing a selected number of consecutive operations of the contacts by a single manual actuation of the operating part H 01 H 41/00)  

11
/ 52 using electromagnetic relays  

11
/ 54 using elements simulating biological cells, e.g. neuron  

11
/ 56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency (counting arrangements comprising multi-stable elements of this type H 03 K 25/00, H 03 K 29/00) [2]  

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