(0)G06F:2/5:

(0)G06F:2/5:

IPC6

SECTION G - PHYSICS

ELECTRIC DIGITAL DATA PROCESSING

G06F

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G06F009/00 - G06F011/34

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Arrangements for programme control, e.g. control unit (programme control for peripheral devices G 06 F 13/10; in regulating or control systems G 05 B) [4]

using wired connections, e.g. plugboard

using record carriers containing only programme instructions (G 06 F 9/06 takes precedence)

using stored programme, i.e. using internal store of processing equipment to receive and retain programme

Micro-control or micro-programme arrangements [3]

Loading of the micro-programme [3]

Address formation of the next micro-instruction (G 06 F 9/28 takes precedence) [3]

Enhancement of operational speed, e.g. by using several micro-control devices operating in parallel [3]

Arrangements for executing machine- instructions, e.g. instruction decode (for executing micro-instructions G 06 F 9/22; for executing subprogrammes G 06 F 9/40) [3]

Controlling the executing of arithmetic operations [5]

Controlling the executing of logical operations [5]

Controlling single bit operations (G 06 F 9/305 takes precedence) [5]

Controlling loading, storing or clearing operations [5]

Controlling moving, shifting or rotation operations [5]

with operation extension or modification [5]

Address formation of the next instruction, e.g. incrementing the instruction counter, jump (G 06 F 9/38 takes precedence; subprogramme jump G 06 F 9/42) [3]

Addressing or accessing the instruction operand or the result (address translation G 06 F 12/00) [3,5]

of multiple operands or results [5]

Indirect addressing [5]

Indexed addressing [5]

Concurrent instruction execution, e.g. pipeline, look ahead [3]

Arrangements for executing subprogrammes, i.e. combinations of several instructions [3]

Formation of subprogramme-jump address or of return address [3]

Arrangements for executing specific programmes [3]

Programme loading or initiating [5]

Compilation or interpretation of high level programme languages [5]

Emulation; Software simulation [5]

Multiprogramming arrangements, e.g. using interrupt; Priority circuits therefor [3]

Error detection; Error correction; Monitoring (methods or arrangements for verifying the correctness of marking on a record carrier G 06 K 5/00 ; in information storage based on relative movement between record carrier and transducer G 11 B, e.g. G 11 B 20/18; in static stores G 11 C; coding, decoding or code conversion, for error detection or error correction, in general H 03 M 13/00) [4]

Error detection or correction by redundancy in data representation, e.g. by using checking codes

Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

Error detection or correction of the data by redundancy in operation (G 06 F 11/16 takes precedence) [3]

Error detection or correction of the data by redundancy in hardware [3]

using passive fault-masking of the redundant circuits, e.g. by quadding or by majority decision circuits [3]

using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements [3]

Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing (testing of digital circuits, e.g. of separate computer components, G 01 R 31/317) [3]

Marginal testing [3]

Testing of logic operation, e.g. by logic analysers [6]

Functional testing [3]

Generation of test inputs, e.g. test vectors, patterns or sequences [6]

Reconfiguring circuits for testing, e.g. LSSD, partitioning [6]

Built-in tests [6]

Tester hardware, i.e. output processing circuits [6]

with comparison between actual response and known fault-free response [6]

by checking the correct order of processing (G 06 F 11/08 to G 06 F 11/277 take precedence; monitoring patterns of pulse trains H 03 K 5/19) [3]

with visual indication of the functioning of the machine [3]

Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation [3]

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